The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2005

Filed:

May. 31, 2002
Applicants:

Jae-hyun Joo, Seoul, KR;

Cha-young Yoo, Suwon, KR;

Wan-don Kim, Kyungki-do, KR;

Yong-kuk Jeong, Seoul, KR;

Inventors:

Jae-hyun Joo, Seoul, KR;

Cha-young Yoo, Suwon, KR;

Wan-don Kim, Kyungki-do, KR;

Yong-kuk Jeong, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8242 ;
U.S. Cl.
CPC ...
Abstract

In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.


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