The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2005
Filed:
Mar. 28, 2003
Applicant:
Anthony J. Toprac, Austin, TX (US);
Inventor:
Anthony J. Toprac, Austin, TX (US);
Assignee:
Yield Dynamics, Inc., Sunnyvale, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B24B001/00 ;
U.S. Cl.
CPC ...
Abstract
A method for planarizing the surface of a semiconductor wafer or device during manufacture. Dependencies of polish rate and substrate thickness on process parameters of downforce and polish speed, and on the characteristic product high feature area on the wafer, are explicitly defined and used to control Chemical-Mechanical Polish in Run-to-Run and real-time semiconductor production control applications.