The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2005
Filed:
Sep. 05, 2003
Chia-ta Hsieh, Tainan, TW;
Yi-jiun Lin, Taipei, TW;
Feng-jia Shiu, Hsinchu, TW;
Hung-cheng Sung, Hsin-chu, TW;
Chi-hsin Lo, Chupei, TW;
Chia-Ta Hsieh, Tainan, TW;
Yi-Jiun Lin, Taipei, TW;
Feng-Jia Shiu, Hsinchu, TW;
Hung-Cheng Sung, Hsin-chu, TW;
Chi-Hsin Lo, Chupei, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.