The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Jul. 06, 2001
Norihiro Kobayashi, Annaka, JP;
Shoji Akiyama, Annaka, JP;
Masaro Tamatsuka, Annaka, JP;
Masaru Shinomiya, Annaka, JP;
Yuichi Matsumoto, Annaka, JP;
Norihiro Kobayashi, Annaka, JP;
Shoji Akiyama, Annaka, JP;
Masaro Tamatsuka, Annaka, JP;
Masaru Shinomiya, Annaka, JP;
Yuichi Matsumoto, Annaka, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
Provided is a process for manufacturing a silicon wafer employing heat treatment which is applied on the silicon wafer in inert gas atmosphere represented by Ar annealing to annihilate Grown-in defects in a surface layer region of the silicon wafer as well as to cause no degradation of haze and micro-roughness on a surface thereof. In a process for manufacturing a silicon wafer having a step of heat treating the silicon wafer in inert gas atmosphere, using a purge box with which the silicon wafer heat treated in the inert gas atmosphere can be unloaded to outside a reaction tube of a heat treatment furnace without being put into contact with the open air, the purge box is filled with mixed gas of nitrogen and oxygen or 100% oxygen gas, and the heat treated silicon wafer is unloaded into the purge box.