The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2005

Filed:

May. 31, 2001
Applicants:

Peter J. Brofman, Hopewell Junction, NY (US);

Glenn G. Daves, Beacon, NY (US);

Sudipta K. Ray, Wappingers Falls, NY (US);

Herbert I. Stoller, Poughkeepsie, NY (US);

Inventors:

Peter J. Brofman, Hopewell Junction, NY (US);

Glenn G. Daves, Beacon, NY (US);

Sudipta K. Ray, Wappingers Falls, NY (US);

Herbert I. Stoller, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/46 ; H01L021/30 ; H01L021/4763 ; H01L021/44 ; H01L021/302 ;
U.S. Cl.
CPC ...
Abstract

A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.


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