The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6870272 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 22, 2005

Filed:

Apr. 16, 2002
Applicants:

Zlata Kovac, Los Alamitos, CA (US);

Craig Mitchell, San Jose, CA (US);

Thomas Distefano, Monte Sereno, CA (US);

John Smith, Horseshoe Bay, TX (US);

Inventors:

Zlata Kovac, Los Alamitos, CA (US);

Craig Mitchell, San Jose, CA (US);

Thomas Distefano, Monte Sereno, CA (US);

John Smith, Horseshoe Bay, TX (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/48 ;
U.S. Cl.
CPC ...
Abstract

An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.


Find Patent Forward Citations

Kovac, Zlata. (2005). Methods of making microelectronic assemblies including compliant interfaces (U.S. Patent No. 6870272). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6870272

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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