The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6869542 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 22, 2005

Filed:

Mar. 12, 2003
Applicants:

Sadanand V. Desphande, Fishkill, NY (US);

David Dobuzinsky, New Windsor, NY (US);

Arpan P. Mahorowala, Bronxville, NY (US);

Tina Wagner, Newburgh, NY (US);

Richard Wise, New Windsor, NY (US);

Inventors:

Sadanand V. Desphande, Fishkill, NY (US);

David Dobuzinsky, New Windsor, NY (US);

Arpan P. Mahorowala, Bronxville, NY (US);

Tina Wagner, Newburgh, NY (US);

Richard Wise, New Windsor, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/00 ;
U.S. Cl.
CPC ...
Abstract

Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N; fluorocarbon (CHF, CF, CF, CF, CHF, CHF); an oxidizer (O, CO), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (−20 to 60°).


Find Patent Forward Citations

Desphande, Sadanand. (2005). Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials (U.S. Patent No. 6869542). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6869542

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