The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2005
Filed:
Nov. 19, 2001
Kilho Lee, Wappingers Falls, NY (US);
Woo-tang Kang, Wappingers Falls, NY (US);
Rajesh Rengarajan, Poughkeepsie, NY (US);
Kilho Lee, Wappingers Falls, NY (US);
Woo-Tang Kang, Wappingers Falls, NY (US);
Rajesh Rengarajan, Poughkeepsie, NY (US);
Infineon Technologies AG, Munich, DE;
Abstract
In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising: a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site; b) forming an undoped polysilicon layer over the gate oxide layer; c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer; d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions; e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; and f) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.