The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2005
Filed:
Feb. 10, 2003
Applicants:
Takanori Hirota, Tokyo, JP;
Atsuhiko Ishibashi, Tokyo, JP;
Inventors:
Takanori Hirota, Tokyo, JP;
Atsuhiko Ishibashi, Tokyo, JP;
Assignee:
Renesas Technology Corp., Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H03L007/06 ;
U.S. Cl.
CPC ...
Abstract
Assuming that clocks in an A clock driver (), a B clock driver () and a CMOS buffer circuit () have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a register circuit () when terminals '0' of selector circuits () are selected, and a delay value Ta−Td−Tb is stored in a register circuit () when the terminals '0' are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit () allows a phase difference between the A clock driver () and B clock driver () to be determined.