The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2005
Filed:
Jan. 29, 2003
Tsuyoshi Koga, Hyogo, JP;
Yoshiyuki Ishigaki, Hyogo, JP;
Motoi Ashida, Hyogo, JP;
Yukio Maki, Hyogo, JP;
Yasuhiro Fujii, Hyogo, JP;
Tomohiro Hosokawa, Hyogo, JP;
Takashi Terada, Hyogo, JP;
Makoto Dei, Hyogo, JP;
Yasuichi Masuda, Hyogo, JP;
Tsuyoshi Koga, Hyogo, JP;
Yoshiyuki Ishigaki, Hyogo, JP;
Motoi Ashida, Hyogo, JP;
Yukio Maki, Hyogo, JP;
Yasuhiro Fujii, Hyogo, JP;
Tomohiro Hosokawa, Hyogo, JP;
Takashi Terada, Hyogo, JP;
Makoto Dei, Hyogo, JP;
Yasuichi Masuda, Hyogo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.