The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2005

Filed:

Dec. 30, 2002
Applicants:

Hung-cheng Sung, Hsinchu, TW;

Han-ping Chen, Hsin-Chu, TW;

Cheng-yuan Hsu, Ma-gou, TW;

Inventors:

Hung-Cheng Sung, Hsinchu, TW;

Han-Ping Chen, Hsin-Chu, TW;

Cheng-Yuan Hsu, Ma-gou, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21336 ; H01L 29788 ;
U.S. Cl.
CPC ...
Abstract

A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.


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