The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
Jan. 29, 2002
Andrew Horch, Sunnyvale, CA (US);
Michael Rowlandson, Portland, OR (US);
Andrew Horch, Sunnyvale, CA (US);
Michael Rowlandson, Portland, OR (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A CMOS memory cell (FIG.) is provided which includes a PMOS transistor () and an NMOS transistor () with a common floating gate and common drains configured to prevent a large drain of Icc current from a power supply during power-up. To prevent the large Icc during power-up, the threshold voltages of the PMOS transistor () and NMOS transistor () are set so that the PMOS transistor () and NMOS transistor () do not turn on together, irrespective of charge initially stored on the floating gate. Without such thresholds, a significant drain of current Icc from the power supply connection Vcc can occur since charge initially on the floating gate leaves both the PMOS transistor () and the NMOS transistor () on creating a path for Icc from Vcc to Vss.