The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
Feb. 10, 2003
Applicants:
Michael Baird, Chandler, AZ (US);
Richard T. Ida, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Hongzhong Xu, Gilbert, AZ (US);
Sopan Joshi, Urbana, IL (US);
Inventors:
Michael Baird, Chandler, AZ (US);
Richard T. Ida, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Hongzhong Xu, Gilbert, AZ (US);
Sopan Joshi, Urbana, IL (US);
Assignee:
Freescale Semiconductor, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2362 ;
U.S. Cl.
CPC ...
Abstract
Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.