The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
May. 02, 2002
Makoto Kitano, Tsuchiura, JP;
Akihiro Yaguchi, Ibaraki-ken, JP;
Naotaka Tanaka, Ibaraki-ken, JP;
Takeshi Terasaki, Ibaraki-ken, JP;
Ichiro Anjoh, Koganei, JP;
Ryo Haruta, Kodaira, JP;
Asao Nishimura, Kokubunji, JP;
Junichi Saeki, Yokohama, JP;
Makoto Kitano, Tsuchiura, JP;
Akihiro Yaguchi, Ibaraki-ken, JP;
Naotaka Tanaka, Ibaraki-ken, JP;
Takeshi Terasaki, Ibaraki-ken, JP;
Ichiro Anjoh, Koganei, JP;
Ryo Haruta, Kodaira, JP;
Asao Nishimura, Kokubunji, JP;
Junichi Saeki, Yokohama, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.