The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Dec. 20, 2002
Cindy K. Goldberg, Grenoble, FR;
Stanley Michael Filipiak, Pflugerville, TX (US);
John C. Flake, Montbonnot, FR;
Yeong-jyh T. Lii, Plano, TX (US);
Bradley P. Smith, Gieres, FR;
Yuri E. Solomentsev, Allen, TX (US);
Terry G. Sparks, Austin, TX (US);
Kirk J. Strozewski, Round Rock, TX (US);
Kathleen C. Yu, Austin, TX (US);
Cindy K. Goldberg, Grenoble, FR;
Stanley Michael Filipiak, Pflugerville, TX (US);
John C. Flake, Montbonnot, FR;
Yeong-Jyh T. Lii, Plano, TX (US);
Bradley P. Smith, Gieres, FR;
Yuri E. Solomentsev, Allen, TX (US);
Terry G. Sparks, Austin, TX (US);
Kirk J. Strozewski, Round Rock, TX (US);
Kathleen C. Yu, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Dummy features () are formed within an interlevel dielectric layer (). Passivation layers (and) are formed by electroless deposition to protect the underlying conductive regions (and) from being penetrated from the air gaps (). In addition, the passivation layers (and) overhang the underlying conductive regions (and), thereby defining dummy features (and) adjacent the conductive regions (and). The passivation layers (and) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.