The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6835622 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 28, 2004

Filed:

Jun. 04, 2002
Applicant:
Inventors:

Ling-Yen Yeh, Taipei, TW;

Jyh-Chyurn Guo, Chutung Hsinchu, TW;

Ih-Chin Chen, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/18234 ;
Abstract

Within a semiconductor fabrication and a method for fabricating the semiconductor fabrication there is provided a series of field effect devices having in a first instance an optional pair of different gate dielectric layer thicknesses, and in a second instance different dopant distribution profiles with respect to a pair of gate electrodes formed upon a pair of gate dielectric layers of a single thickness. The method provides the semiconductor fabrication with multiple gate dielectric layer thicknesses, actual and effective, with enhanced manufacturability and reliability.


Find Patent Forward Citations

Yeh, Ling-Yen. (2004). Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses (U.S. Patent No. 6835622). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6835622

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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