The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6828198 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 07, 2004

Filed:

Mar. 19, 2003
Applicant:
Inventors:

Hung-Der Su, Kao-Hsiung Country, TW;

Shien-Yang Wu, Hsin chu, TW;

Yung-Shun Chen, Hsin-chu, TW;

Tung-Heng Shie, Hsinchu, TW;

Yuan-Hung Chiu, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.


Find Patent Forward Citations

Su, Hung-Der. (2004). System-on-chip (soc) solutions with multiple devices by multiple poly gate trimming process (U.S. Patent No. 6828198). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6828198

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