Method of detecting and distinguishing stack gate edge defects at the source or drain junction

Abstract

A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed ( ). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions ( ). Subsequent to the stressing, a drain current versus gate voltage relationship is measured ( ). The sequence of programming, stressing and measuring may be repeated ( ) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified ( ) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.