The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2004
Filed:
Dec. 13, 2002
Der-Shin Shyu, Hsinchu, TW;
Hung-Cheng Sung, Hsin-chu, TW;
Li-Wen Chang, Taipei, TW;
Han-Ping Chen, Hsin-Chu, TW;
Chen-Ming Huang, Jungli, TW;
Ya-Chen Kao, Taoyuan, TW;
Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;
Abstract
A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.