The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2004
Filed:
Mar. 04, 2002
Thomas W. Williams, Boulder, CO (US);
Peter Wohl, Williston, VT (US);
John A. Waicukauski, Tualatin, OR (US);
Rohit Kapur, Cupertino, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.