The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2004

Filed:

Aug. 15, 2002
Applicant:
Inventors:

Yoshinao Taketomi, Kytanabe, JP;

Keizaburo Kuramasu, Kyotanabe, JP;

Masumi Izuchi, Hirakata, JP;

Hiroshi Satani, Yawata, JP;

Hiroshi Tsutsu, Osaka, JP;

Hikaru Nishitani, Nara, JP;

Mikihiko Nishitani, Nara, JP;

Masashi Goto, Moriguchi, JP;

Yoshiko Mino, Nara, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 3/1036 ;
U.S. Cl.
CPC ...
H01L 3/1036 ;
Abstract

In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate . In the insulation layer, a lower insulation layer , which is in contact with the transparent insulating substrate , is made to have a higher thermal conductivity than an upper insulation layer . Thereafter, the upper insulation layer is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer . Thus, the amorphous silicon thin film is formed into a polycrystalline silicon thin film


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