The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2004
Filed:
May. 31, 2001
Applicant:
Inventors:
Stanford W. Crane, Jr., Santa Clara, CA (US);
Myoung-soo Jeon, Fremont, CA (US);
Charley Takeshi Ogata, San Jose, CA (US);
Ton-Yong Wang, Fremont, CA (US);
Andreas C. Cangellaris, Champaign, IL (US);
Jose Schutt-Aine, Savoy, IL (US);
Assignee:
Silicon Bandwidth Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract
A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.