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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6797442 B1

PDFFull Text
Date of Patent:
Sep. 28, 2004

Filed:

Jul. 09, 2003

Fabrication method of semiconductor integrated circuit device

Applicant:
Inventors:

Kazuyuki Tokorozuki, Hitachinaka, JP;

Tetsuji Yokouchi, Hitachinaka, JP;

Yoshiyuki Miyamoto, Takasaki, JP;

Koji Yamamoto, Ome, JP;

Assignee:

Renesas Technology Corp., Tokyo, JP;

Attorney:

Miles & Stockbridge P.C.

Primary Examiner:

David Nelms

Assistant Examiner:

David Vu

Int. Cl.
CPC ...
G03F 9/00 ;
U.S. Cl.
CPC ...
G03F 9/00 ;
Abstract

An average value of dimensions of resist patterns formed each time exposure processing is effected on semiconductor substrates of a predetermined number of lots, is compared with a target dimension. When a drift between each of the dimensions of the formed resist patterns and the target dimension is larger than a first value, exposure energy is corrected with a relatively large correction value &agr; . When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the first value and larger than a second value, exposure energy is corrected with a relatively small correction value &agr; . When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the second value, no exposure energy is corrected. Exposure processing is effected on a semiconductor substrate of the next lot by using the calculated exposure energy.

Find Patent Forward Citations

Tokorozuki, Kazuyuki. (2004). Fabrication method of semiconductor integrated circuit device (U.S. Patent No. 6797442). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6797442

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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