The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2004

Filed:

Nov. 20, 2002
Applicant:
Inventors:

Brian E. Stine, Santa Clara, CA (US);

David M. Stashower, Los Gatos, CA (US);

Sherry F. Lee, San Jose, CA (US);

Kurt H. Weiner, San Jose, CA (US);

Assignee:

PDF Solutions, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 ; G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 9/45 ; G06F 1/750 ;
Abstract

A system and method for predicting yield of integrated circuits includes a characterization vehicle ( ) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle ( ) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model ( ). The yield model ( ) embodies a layout as defined by the characterization vehicle ( ) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine ( ) extracts predetermined layout attributes ( ) from a proposed product layout ( ). Operating on the yield model, the extraction engine ( ) produces yield predictions ( ) as a function of layout attributes ( ) and broken down by layers or steps in the fabrication process ( ).


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