The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2004
Filed:
Aug. 15, 2002
David C. Gilmer, Austin, TX (US);
Christopher C. Hobbs, Austin, TX (US);
Hsing-Huang Tseng, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor device ( ) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric ( ) is formed in a region of the device for higher voltage requirements, e.g. an I/O region ( ). A thinner second gate dielectric ( ) is formed in a region of the device for lower voltage requirements, e.g. a core device region ( ). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide ( ) is deposited over both dielectrics, followed by deposition of a gate electrode material ( ). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.