The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2004

Filed:

Jan. 14, 2003
Applicant:
Inventors:

Chung-Yi Chen, Taipei Hsien, TW;

Jih-Wen Chou, Hsin-Chu, TW;

Chih-Hsun Chu, Hsin-Chu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18234 ;
Abstract

A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.


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