The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2004

Filed:

Oct. 10, 2002
Applicant:
Inventor:

Seiya Suzuki, Atsugi, JP;

Assignee:

Anritsu Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/500 ; G11B 9/00 ; H04L 7/27 ; H04L 2/502 ;
U.S. Cl.
CPC ...
G06F 1/500 ; G11B 9/00 ; H04L 7/27 ; H04L 2/502 ;
Abstract

The present invention provides a measuring device which extracts, from an inputted data signal, a clock signal in which there is little internal occurrence of absence or phase fluctuations, and correctly carries out measurement of an error ratio or jitter or wander accompanying transmission of the data signal by using the clock signal. A band-pass filter extracts, from the inputted data signal, a signal component having a same frequency as that of a clock signal to be regenerated. A binarizing circuit binarizes the extracted signal component at a predetermined threshold value, and outputs it as a regenerated clock signal. At this time, the binarizing circuit is configured such that, when there is a same code continuing period in the data signal, the binarizing circuit binarizes the signal outputted during the period by relaxation vibration at an interior of the band-pass filter, so as to compensate for absence of the clock signal during the period. A calculating module calculates at least one of the error ratio, the jitter, and the wander based on the regenerated clock signal from the binarizing circuit.


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