The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2004
Filed:
Jan. 04, 2002
Applicant:
Inventor:
Hsueh-Heng Liu, Kaohsiung, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/182 ; H01L 2/128 ;
U.S. Cl.
CPC ...
H01L 2/182 ; H01L 2/128 ;
Abstract
A method for forming an antifuse interconnect structure, for a one-time fusible link, with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the sidewalls of the amorphous silicon layer protected by critical silicon nitride sidewall spacers, during the patterning/etch procedure of the overlying metal layer. The protective sidewall spacers prevent the amorphous Si antifuse from being etched by subsequent processes.
Liu, Hsueh-Heng. (2004). Method to prevent antifuse si damage using sidewall spacers (U.S. Patent No. 6773967). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6773967
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile