The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Dec. 20, 2000
Applicant:
Inventors:

Hiroaki Matsuyama, Tokyo, JP;

Kiyomi Kawada, Tokyo, JP;

Seiji Suzuki, Tokyo, JP;

Yoshihiko Hirai, Tokyo, JP;

Michiaki Sakamoto, Tokyo, JP;

Mamoru Okamoto, Tokyo, JP;

Yuji Yamamoto, Tokyo, JP;

Toshiya Ishii, Tokyo, JP;

Teruaki Suzuki, Tokyo, JP;

Ken Sumiyoshi, Tokyo, JP;

Masayoshi Suzuki, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/1337 ;
U.S. Cl.
CPC ...
G02F 1/1337 ;
Abstract

In an orientation division type liquid crystal display device for widen a viewing angle of a display pixel of an active matrix type liquid crystal color display device having a COT structure, pixel color layers ( B, R, G) as color filters and pixel electrodes are formed on a substrate on the side of the pixel electrodes and slopes are provided along four side peripheries of each pixel electrode. Liquid crystal molecules between each pixel electrode of the pixel electrode substrate and a common electrode of an opposing substrate are controlled in orientation direction along the slopes to divide it to a plurality of directions to thereby widen a viewing angle of a pixel display. The slope is formed on a step portion formed by a BM layer formed on at least one of a gate electrode, a drain electrode and a source electrode formed in a periphery of the pixel electrode or at least one of a gate wiring and a drain wiring formed in the periphery or a step portion formed by partially overlapping peripheral portions of the adjacent pixel color layers.


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