The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Sep. 06, 2001
Applicant:
Inventor:

Yasutaka Tsuruki, Tokyo, JP;

Assignee:

Advantest Corp., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract

A timing signal generation circuit comprising: a negative feedback loop comprising; a variable delay circuit for outputting a timing signal delayed from an input clock signal by a delay amount designated by a delay code; a phase difference detector for detecting a phase difference between the timing signal and the input clock signal to output a detection signal; and a loop filter for smoothing a waveform of the detection signal to generate a voltage signal and for feeding the voltage signal back to the variable delay circuit: and a cancel unit for generating a reverse detection signal based on the delay code to cancel the phase difference caused by a change in the delay amount where the reverse detection signal is supplied to the low pass filter.


Find Patent Forward Citations

Tsuruki, Yasutaka. (2004). Timing signal generation circuit and semiconductor test device with the same (U.S. Patent No. 6768360). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6768360

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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