The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2004
Filed:
Jun. 22, 2001
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-chu, TW;
Abstract
An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.