The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2004
Filed:
Jul. 28, 1999
Kazuo Nakazato, Cambridge, GB;
Kiyoo Itoh, Tokyo, JP;
Hiroshi Mizuta, Tokyo, JP;
Toshihiko Sato, Cambridge, GB;
Toshikazu Shimada, Tokyo, JP;
Haroon Ahmed, Cambridge, GB;
Hitachi, LTD., Tokyo, JP;
Abstract
A memory device includes a memory node ( ) to which charge is written through a tunnel barrier configuration ( ) from a control electrode ( ). The stored charge effects the conductivity of a source/drain path ( ) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers ( ) of polysilicon of 3 nm thickness and layers ( ) of Si N of 1 nm thickness, overlying polycrystalline layer of silicon ( ) which forms the memory node. Alternative barrier configurations ( ) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands ( ), which act as the memory node, distributed in an electrically insulating matrix.