The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2004

Filed:

Nov. 08, 2001
Applicant:
Inventors:

Steve K. Hsia, San Jose, CA (US);

Kyung Joon Han, Palo Alto, CA (US);

Dung Tran, San Jose, CA (US);

Assignee:

NexFlash Technologies, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.


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