The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2004
Filed:
Jan. 10, 2002
Kuo-Tso Chen, Hsinchu, TW;
Chi-Ming Liu, Taoyuan, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method and apparatus for estimating burn-in time for integrated circuit die on a wafer employs a reliability testing structure placed in a scribe line area of a wafer to permit improved estimation of burn-in time for integrated circuit on a wafer. Each reliability testing structure has a plurality of evaluation device structures formed on the substrate. Groups of the evaluation device structures are stacked on the surface of the substrate. The device structures are created to permit evaluation of one of a plurality of failure mechanisms of the integrated circuit. A forcing input pad and a sensing output pad are connected through a selection circuit to at least one of the evaluation devices. The selection circuit selects which of the evaluation devices are to receive a stimulus and to transmit a response. The stimulus is activated and the substrate is then stressed. Each selected evaluation device structure is examined for failure and the hazard rate for each failure mechanism of the integrated circuit is determined and from the hazard rate the burn-in time for the integrated circuit is calculated.