The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6743686 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 01, 2004

Filed:

Jun. 14, 2002
Applicant:
Inventors:

Kam Leung Lee, Putnam Valley, NY (US);

Ying Zhang, Yorktown Heights, NY (US);

Maheswaran Surendra, Croton-on-Hudson, NY (US);

Edmund M. Sikorski, Florida, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.


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Lee, Kam. (2004). Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance cmos fabrication (U.S. Patent No. 6743686). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6743686

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