Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement

Abstract

A first clock stage in a circuit utilizes a second stage clock for triggering the falling edge of a first clock stage output. The output will not reset until both the first clock is low and the second clock are high due to the addition of the second clock signal. This is accomplished by adding a transistor and inverter to the first stage. The drain of a P-type FET is connected to source of the P-FET being controlled by the first clock through its gate. The additional P-FET is controlled by an inverted second clock signal. The clock signal is inverted by an inverter connected to the gate of the additional P-FET. Stability is provided to the first stage by creating a full keeper, which holds the output from the logic device in the first stage. A pair of transistors are connected by their drains to the output of the logic device. The transistors are controlled by an inverter, which is connected to the pairs' bases, wherein the inverter receives the output from the logic device. The transistor pair comprises one N-FET and P-FET.