The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2004

Filed:

Apr. 19, 2002
Applicant:
Inventors:

Hsiao-Han Thio, Sunnyvale, CA (US);

Nian Yang, San Jose, CA (US);

Zhigang Wang, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18238 ; H01L 2/176 ; H01L 2/13205 ; H01L 2/1311 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 2/18238 ; H01L 2/176 ; H01L 2/13205 ; H01L 2/1311 ;
Abstract

A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.


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