The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2004

Filed:

Mar. 15, 2002
Applicant:
Inventors:

Yasuhiko Onishi, Nagano, JP;

Tatsuhiko Fujihira, Nagano, JP;

Katsunori Ueno, Nagano, JP;

Susumu Iwamoto, Nagano, JP;

Takahiro Sato, Nagano, JP;

Tatsuji Nagaoka, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
Abstract

To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.


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