The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
May. 20, 1997
Trung T. Doan, Boise, ID (US);
Randhir P. S. Thakur, Boise, ID (US);
Yauh-Ching Liu, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A multilayer heterostructure is provided a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). A barrier film having a structural integrity is superjacent the planarization layer. A second layer is formed superjacent the barrier film. The second layer comprises tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). Heating causes the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step. Further, the planarization layer goes through a solid state reaction and the second layer obtains a uniform reflow.