The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2004
Filed:
May. 10, 2001
National Science Council, Taipei, TW;
Abstract
In the fabrication of gate oxides in IC process, a suitable cleaning/etching process is required to remove the native oxides and reduce surface microroughness in addition to standard RCA cleaning. For ultrathin oxide thickness (<10 nm), it is an important issue to have a native-oxide-free and H-passivated silicon (Si) surface to ensure high breakdown field, high charge-to-breakdown, and low leakage current. According to these concepts, we propose an invention with a simple two-step hydrogen fluoride (HF) etching process to improve the electrical properties of liquid-phase deposited fluorinated silicon oxides (LPD-SiOF), including effective removal of native oxides, lowering of interface trap density (˜10 eV−1 cm ), reduction of surface microroughness (Ra=0.1 nm), and raising of breakdown field (˜9.7 MV/cm). Furthermore, rapid thermal annealing (RTA) is also used to further improve the oxide quality. It is found that 18% increase of breakdown field and 33% reduction of interface trap density can be reached. In addition to the suitability for LPD-silicon oxides (SiO ), this technique is also suitable to other doped oxides. This technology is helpful to obtain a high quality and low cost silicon oxide for the ultrathin gate oxide in the future ULSI process.