The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2004

Filed:

Apr. 26, 2002
Applicant:
Inventor:

Hideo Takeuchi, Tokyo, JP;

Assignee:

Advantest Corp., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/126 ;
U.S. Cl.
CPC ...
G01R 3/126 ;
Abstract

The apparatus includes: a sequencer for outputting a start signal, a timing signal, a write-in signal, and a clock signal sequentially, when an AD start signal is input; an ADC for measuring an output of a device under test (DUT) to which a test pattern is input, when the start signal is input; an arithmetic/logical unit (ALU) for outputting an output voltage value of the ADC when the timing signal is input, and for outputting a result of comparing the output voltage value with an expected value to the pattern generator as a PASS/FAIL signal; an address counter for updating an address value to be output when the clock signal is input; and a history memory for storing a measurement value in an address indicated by the address value when the write-in signal is input. This configuration makes it possible to measure each voltage value output from the DUT for a test pattern corresponding each AD start signal.


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