The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2004
Filed:
Jun. 24, 2002
Kazuhisa Arai, Tokyo, JP;
Masaya Takeuchi, Tokyo, JP;
Hiromi Hayashi, Tokyo, JP;
Hideyuki Sando, Tokyo, JP;
Disco Corporation, Tokyo, JP;
Abstract
A semiconductor wafer dividing method for dividing a semiconductor wafer, in which a plurality of rectangular regions are demarcated by streets arranged in a lattice pattern on the face of the semiconductor wafer, and a semiconductor circuit is disposed in each of the rectangular regions, into the individual rectangular regions. This method includes a groove cutting step of cutting the face of the semiconductor wafer along the streets to form grooves along the streets on the face of the semiconductor wafer, and a back grinding step of grinding the back of the semiconductor wafer to reduce the thickness of the semiconductor wafer to not more than the depth of the grooves, thereby dividing the semiconductor wafer along the streets. This method further includes, before the back grinding step, a groove depth measuring step of measuring the depth of the grooves. In the back grinding step, rough grinding is performed until the thickness of the semiconductor wafer becomes greater than the depth of the grooves by a predetermined value, and then precision grinding is performed until the thickness of the semiconductor wafer becomes not more than the depth of the grooves.