The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2004

Filed:

Feb. 28, 2001
Applicant:
Inventors:

Shan Sun, Colorado Springs, CO (US);

George Hickert, Colorado Springs, CO (US);

Katsuyoshi Matsuura, Kanagawa, JP;

Takeyasu Saito, Kanagawa, JP;

Soichiro Ozawa, Kanagawa, JP;

Naoyuki Satoh, Kanagawa, JP;

Mitsushi Fujiki, Kanagawa, JP;

Satoru Mihara, Kanagawa, JP;

Jeffrey S. Cross, Kanagawa, JP;

Yoshimasa Horii, Kanagawa, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01G 4/06 ;
U.S. Cl.
CPC ...
H01G 4/06 ;
Abstract

A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr Ru O , on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr Ru O . The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.


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