Method and apparatus for a deposited fill layer

Abstract

A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.