The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2003
Filed:
Dec. 14, 2001
Applicant:
Inventors:
Om P. Agrawal, Los Altos, CA (US);
Jinghui Zhu, San Jose, CA (US);
Kuang Chi, San Jose, CA (US);
ChienKuang Chen, Sunnyvale, CA (US);
Assignee:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/500 ; H03L 7/06 ;
U.S. Cl.
CPC ...
H01L 2/500 ; H03L 7/06 ;
Abstract
A programmable interconnect circuit includes a phase-locked loop configured to provide an internal clock signal to I/O cells in the programmable interconnect circuit such that registers in the I/O cells may all be clocked in phase. In addition, the phase-locked loop may provide an external clock signal to the programmable interconnect circuit's routing structure such that external devices may clocked in phase with the external clock signal.