Structure and method for wafer comprising dielectric and semiconductor

Abstract

Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planarization (CMP) is performed to remove a portion of the dielectric layer, exposing the upper surfaces of the semiconductor regions. The amount of CMP necessary to expose all of the semiconductor regions on the wafer is reduced, because the dielectric is targeted to deposit up to the upper edge of the semiconductor regions in the spaces in between the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer. The thickness of the dielectric or semiconductor layer deposited on polish monitor pads located at the edges of each die may be monitored to determine when enough CMP has been performed to expose each of the semiconductor regions.