The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2003

Filed:

Oct. 18, 2000
Applicant:
Inventors:

Thomas George Ference, Essex Junction, VT (US);

Wayne John Howell, Williston, VT (US);

Edmund Juris Sprogis, Underhill, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/148 ; H01L 2/150 ; H01L 2/348 ; H01L 2/352 ; H01L 2/940 ; H01L 2/334 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/148 ; H01L 2/150 ; H01L 2/348 ; H01L 2/352 ; H01L 2/940 ; H01L 2/334 ;
Abstract

Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.


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