The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2003

Filed:

Oct. 17, 2002
Applicant:
Inventors:

Atsushi Kanda, Suwa, JP;

Yasushi Haga, Sakata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

Among first and second oxide films and formed on a substrate the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film to define a side wall is subsequently formed on the whole surface of the substrate and a resist R is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films and are then etched off with a resist R B. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R B is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be formed efficiently on an identical substrate without damaging the characteristics of the respective MOS transistors.


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