The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2003
Filed:
Jan. 29, 2002
Michael Rowlandson, Portland, OR (US);
Andrew Horch, Sunnyvale, CA (US);
Lattice Semiconductor Corporation, Hillsboro, CA (US);
Abstract
A non-volatile memory cell (FIG. ) is provided which includes three transistors, a floating gate non-volatile storage transistor ( ) and two cascode connected select transistors ( ). The two cascoded select transistors ( ) act together to block the programming voltage when the memory cell is included in an array, and the memory cell is not selected for programming. A value of an unselect voltage applied to the gate of the first cascode connected transistor ( ) is set to prevent breakdown of the oxide in the first cascode transistor ( ) as well as the second cascode transistor ( ). A value of an unselect voltage applied to the gate of the second cascode connected transistor ( ) can be selected so that the voltage passed to the floating gate storage transistor ( ) will not result in a program drain disturb, or source disturb condition.