Structure to reduce the degradation of the q value of an inductor caused by via resistance

Abstract

A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias. The invention can further be extended by creating at least one second via through the thick layer of polyimide aligned with at least one of the created first vias. A patterned and etched layer of metal that fills the second via creates a re-distribution layer on the surface of the thick layer of polyimide for flip chip interconnects.